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Chip multiprocessors have been the mainstream in computer architecture. Such processors have more than one core on a single chip to obtain higher performance and lower power consumption. However�� when more and more cores are integated onto the chip�� the increasing number of cores makes the communication become the center of the on-chip architecture. It has become a new challenge on how to utilize these integrated cores in a single area with high efficiency. This book provides the explorative research on the above problems. There are four main topics discussed in this book. The first is the hybrid on-chip structure�� which consists of the on-chip network and the on-chip bus. The bus is used to connect the local neighbours�� and the network is used to connect the remote nodes. And then this book provides discussions on on-chip structure and optimizations including the dynamic reconfigurable network�� the design of critical path-driven routers and the transmission bypass optimization. They are used to achieve better performance. The third topic focuses on the on-chip memory design�� which is called the on-chip networked memory system. The memories are connected by the network with distributed memory management units. At last�� the mapping algorithms are discussed�� which aim to map the tasks to the on-chip cores with high efficiency and low-power consumption. This book has provided some works innetwork-based manycore systems. The designs and algorithms provided in this book are potential solutions for multicore/manycore architecture. It can be used as the reference for future work and for the researchers who focus on the computer architecture.

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ContentsPreface1 Introduction to NoC 11.1 Development of Computer Architecture 11.2 Chip Multiprocessor 31.3 On-chip Structure and NoC 61.4 Summary 102 Hybrid Network and Bus On-Chip Interconnection 112.1 Introduction 112.2 Hybrid On-chip Interconnection with NoC and the Bus 132.2.1 Motivation 132.2.2 On-Chip Structure 142.2.3 Support for Thread Scheduling 152.2.4 Experiments and Results 162.3 Dynamic Configurable On-Qiip Network with the Hybrid Bus and Networks 182.3.1 Motivation 182.3.2 Bus/NoC Hybrid Interconnection 192.3.3 Component Design 212.3.4 Experiment and Results 232.4 Summary 283 On-Chip Structure and Optimizations 303.1 Introduction 303.2 Dynamic Reconfigurable Networks for I/O-Supported Parallel Applications 313.2.1 Background 313.2.2 Architecture Design 333.2.3 Implementation 373.2.4 Experiments and Analysis 423.3 Critical Path-Driven Routers for the On-Chip Network 463.3.1 Background 463.3.2 Motivation 483.3.3 Architecture 513.3.4 Implementation 533.3.5 Experiments and Analysis 563.4 Transmission Bypass Optimization for On-Chip Cores 603.4.1 Background 603.4.2 Motivation 613.4.3 Design 623.4.4 Implementation 653.4.5 Experiments and Analysis 683.5 Summary 754 On-Chip Networked Memory System for NoC 774.1 Introduction 774.2 Network Main Memory Architecture for NoC 784.2.1 Background 784.2.2 Motivation 804.2.3 Basic NMM Architecture 814.2.4 Management of NMM and Software Model 854.2.5 Experiments and Analysis 874.3 Distributed Memory Management Units Architecture for NoC 944.3.1 Background 944.3.2 Motivation 984.3.3 Architecture Model 1004.3.4 Experiments and Analysis 1044.4 Summary 1085 Efficient Task Mapping Algorithm with Low-Power Design for NoC 1105.1 Introduction 1105.2 Efficient Task Mapping Algorithm with Power-Aware Optimization for NoC 1115.2.1 Background Ill5.2.2 Motivation 1125.2.3 System Model 1145.2.4 Proposed Algorithm Design 1195.2.5 Experiments and Analysis 1295.3 Energy-Efficient Design of the Microkernel-Based On-Chip OS for NoC 1335.3.1 Background 1335.3.2 Motivation 1345.3.3 Design Overview 1365.3.4 Distributed On-Chip Operating System 1395.3.5 Experimental Results and Analysis 1445.4 Summary 1516 Conclusions 153References 156

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