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数字设计和计算机体系结构 -(英文版.第2版.RRM版) 版权信息
- ISBN：9787111586791
- 条形码：9787111586791 ; 978-7-111-58679-1
- 装帧：一般胶版纸
- 册数：暂无
- 重量：暂无
- 所属分类：>>
数字设计和计算机体系结构 -(英文版.第2版.RRM版) 本书特色
本书采用ARM取代了早先使用MIPS作为核心处理器来介绍计算机组织和设计的基本概念，涵盖了数字逻辑设计的主要内容。本书以一种流行的方式介绍了从计算机组织和设计到更细节层次的内容，涵盖了数字逻辑设计的主要内容，并通过ARM微处理器的设计强化数字逻辑的概念。本书的典型特色是将数字逻辑和计算机体系结构融合，教学内容反映了当前数字电路设计的主流方法，并突出计算机体系结构的工程特点，书中的大量示例及习题也可以加强读者对基本概念和技术的理解和记忆。
数字设计和计算机体系结构 -(英文版.第2版.RRM版) 内容简介
本书采用ARM取代了早先使用MIPS作为核心处理器来介绍计算机组织和设计的基本概念，涵盖了数字逻辑设计的主要内容。本书以一种流行的方式介绍了从计算机组织和设计到更细节层次的内容，涵盖了数字逻辑设计的主要内容，并通过ARM微处理器的设计强化数字逻辑的概念。本书的典型特色是将数字逻辑和计算机体系结构融合，教学内容反映了当前数字电路设计的主流方法，并突出计算机体系结构的工程特点，书中的大量示例及习题也可以加强读者对基本概念和技术的理解和记忆。
数字设计和计算机体系结构 -(英文版.第2版.RRM版) 目录
Contents
Preface . vi
Features . vii
Online Supplements viii
How to Use the Software Tools in a Course ix
Labs ix
Bugs x
Acknowledgments xi
Chapter 1 From Zero to One 3
1.1 TheGamePlan 3
1.2 The Art of Managing Complexity . 4
1.2.1 Abstraction 4
1.2.2 Discipline 5
1.2.3 The Three-Y’s 6
1.3 The Digital Abstraction 7
1.4 Number Systems. 9
1.4.1 Decimal Numbers 9
1.4.2 Binary Numbers 9
1.4.3 Hexadecimal Numbers . 11
1.4.4 Bytes, Nibbles, and All That Jazz . 13
1.4.5 Binary Addition . 14
1.4.6 Signed Binary Numbers 15
1.5 Logic Gates 19
1.5.1 NOT Gate 20
1.5.2 Buffer 20
1.5.3 AND Gate 20
1.5.4 OR Gate . 21
1.5.5 Other Two-Input Gates 21
1.5.6 Multiple-Input Gates . 21
1.6 Beneath the Digital Abstraction 22
1.6.1 Supply Voltage 22
1.6.2 Logic Levels 22
1.6.3 Noise Margins 23
1.6.4 DC Transfer Characteristics 24
1.6.5 The Static Discipline . 24
1.7 CMOSTransistors 26
1.7.1 Semiconductors 27
1.7.2 Diodes 27
1.7.3 Capacitors 28
1.7.4 nMOS and pMOS Transistors 28
1.7.5 CMOS NOT Gate . 31
1.7.6 Other CMOS Logic Gates . 31
1.7.7 Transmission Gates 33
1.7.8 Pseudo-nMOS Logic . 33
1.8 Power Consumption 34
1.9 Summary and a Look Ahead 35
Exercises 37
Interview Questions . 52
Chapter 2 Combinational Logic Design 55
2.1 Introduction 55
2.2 BooleanEquations 58
2.2.1 Terminology 58
2.2.2 Sum-of-Products Form . 58
2.2.3 Product-of-Sums Form . 60
2.3 BooleanAlgebra 60
2.3.1 Axioms . 61
2.3.2 Theorems of One Variable . 61
2.3.3 Theorems of Several Variables 62
2.3.4 The Truth Behind It All 64
2.3.5 Simplifying Equations 65
2.4 From Logic to Gates 66
2.5 Multilevel Combinational Logic 69
2.5.1 Hardware Reduction . 70
2.5.2 Bubble Pushing 71
2.6 X’s and Z’s, Oh My 73
2.6.1 Illegal Value: X . 73
2.6.2 Floating Value: Z 74
2.7 Karnaugh Maps 75
2.7.1 Circular Thinking . 76
2.7.2 Logic Minimization with K-Maps . 77
2.7.3 Don't Cares . 81
2.7.4 The Big Picture 82
2.8 Combinational Building Blocks 83
2.8.1 Multiplexers . 83
2.8.2 Decoders . 86
2.9 Timing. 88
2.9.1 Propagation and Contamination Delay 88
2.9.2 Glitches . 92
2.10 Summary 95
Exercises 97
Interview Questions 106
Chapter 3 Sequential Logic Design 109
3.1 Introduction. 109
3.2 Latches and Flip-Flops . 109
3.2.1 SR Latch . 111
3.2.2 D Latch 113
3.2.3 D FIip-Flop . 114
3.2.4 Register . 114
3.2.5 Enabled Flip-Flop . 115
3.2.6 Resettable Flip-Flop 116
3.2.7 Transistor-Level Latch and Flip-Flop Designs 116
3.2.8 Putting It All Together . 118
3.3 Synchronous Logic Design 119
3.3.1 Some Problematic Circuits 119
3.3.2 Synchronous Sequential Circuits 120
3.3.3 Synchronous and Asynchronous Circuits . 122
3.4 Finite State Machines 123
3.4.1 FSM Design Example 123
3.4.2 State Encodings . 129
3.4.3 Moore and Mealy Machines 132
3.4.4 Factoring State Machines . 134
3.4.5 Deriving an FSM from a Schematic . 137
3.4.6 FSM Review 140
3.5 Timing of Sequential Logic . 141
3.5.1 The Dynamic Discipline 142
3.5.2 System Timing 142
3.5.3 Clock Skew . 148
3.5.4 Metastability 151
3.5.5 Synchronizers . 152
3.5.6 Derivation of Resolution Time 154
3.6 Parallelism 157
3.7 Summary . 161
Exercises 162
Interview Questions 171
Chapter 4 Hardware Description Languages 173
4.1 Introduction. 173
4.1.1 Modules 173
4.1.2 Language Origins . 174
4.1.3 Simulation and Synthesis . 175
4.2 Combinational Logic. 177
4.2.1 Bitwise Operators . 177
4.2.2 Comments and White Space 180
4.2.3 Reduction Operators . 180
4.2.4 Conditional Assignment 181
4.2.5 Internal Variables . 182
4.2.6 Precedence 184
4.2.7 Numbers 185
4.2.8 Z’s and X’s . 186
4.2.9 Bit Swizzling 188
4.2.10 Delays 188
4.3 Structural Modeling 190
4.4 Sequential Logic . 193
4.4.1 Registers 193
4.4.2 Resettable Registers 194
4.4.3 Enabled Registers 196
4.4.4 Multiple Registers . 197
4.4.5 Latches . 198
4.5 MoreCombinationalLogic. 198
4.5.1 Case Statements . 201
4.5.2 If Statements 202
4.5.3 Truth Tables with Don’t Cares . 205
4.5.4 Blocking and Nonblocking Assi
Preface . vi
Features . vii
Online Supplements viii
How to Use the Software Tools in a Course ix
Labs ix
Bugs x
Acknowledgments xi
Chapter 1 From Zero to One 3
1.1 TheGamePlan 3
1.2 The Art of Managing Complexity . 4
1.2.1 Abstraction 4
1.2.2 Discipline 5
1.2.3 The Three-Y’s 6
1.3 The Digital Abstraction 7
1.4 Number Systems. 9
1.4.1 Decimal Numbers 9
1.4.2 Binary Numbers 9
1.4.3 Hexadecimal Numbers . 11
1.4.4 Bytes, Nibbles, and All That Jazz . 13
1.4.5 Binary Addition . 14
1.4.6 Signed Binary Numbers 15
1.5 Logic Gates 19
1.5.1 NOT Gate 20
1.5.2 Buffer 20
1.5.3 AND Gate 20
1.5.4 OR Gate . 21
1.5.5 Other Two-Input Gates 21
1.5.6 Multiple-Input Gates . 21
1.6 Beneath the Digital Abstraction 22
1.6.1 Supply Voltage 22
1.6.2 Logic Levels 22
1.6.3 Noise Margins 23
1.6.4 DC Transfer Characteristics 24
1.6.5 The Static Discipline . 24
1.7 CMOSTransistors 26
1.7.1 Semiconductors 27
1.7.2 Diodes 27
1.7.3 Capacitors 28
1.7.4 nMOS and pMOS Transistors 28
1.7.5 CMOS NOT Gate . 31
1.7.6 Other CMOS Logic Gates . 31
1.7.7 Transmission Gates 33
1.7.8 Pseudo-nMOS Logic . 33
1.8 Power Consumption 34
1.9 Summary and a Look Ahead 35
Exercises 37
Interview Questions . 52
Chapter 2 Combinational Logic Design 55
2.1 Introduction 55
2.2 BooleanEquations 58
2.2.1 Terminology 58
2.2.2 Sum-of-Products Form . 58
2.2.3 Product-of-Sums Form . 60
2.3 BooleanAlgebra 60
2.3.1 Axioms . 61
2.3.2 Theorems of One Variable . 61
2.3.3 Theorems of Several Variables 62
2.3.4 The Truth Behind It All 64
2.3.5 Simplifying Equations 65
2.4 From Logic to Gates 66
2.5 Multilevel Combinational Logic 69
2.5.1 Hardware Reduction . 70
2.5.2 Bubble Pushing 71
2.6 X’s and Z’s, Oh My 73
2.6.1 Illegal Value: X . 73
2.6.2 Floating Value: Z 74
2.7 Karnaugh Maps 75
2.7.1 Circular Thinking . 76
2.7.2 Logic Minimization with K-Maps . 77
2.7.3 Don't Cares . 81
2.7.4 The Big Picture 82
2.8 Combinational Building Blocks 83
2.8.1 Multiplexers . 83
2.8.2 Decoders . 86
2.9 Timing. 88
2.9.1 Propagation and Contamination Delay 88
2.9.2 Glitches . 92
2.10 Summary 95
Exercises 97
Interview Questions 106
Chapter 3 Sequential Logic Design 109
3.1 Introduction. 109
3.2 Latches and Flip-Flops . 109
3.2.1 SR Latch . 111
3.2.2 D Latch 113
3.2.3 D FIip-Flop . 114
3.2.4 Register . 114
3.2.5 Enabled Flip-Flop . 115
3.2.6 Resettable Flip-Flop 116
3.2.7 Transistor-Level Latch and Flip-Flop Designs 116
3.2.8 Putting It All Together . 118
3.3 Synchronous Logic Design 119
3.3.1 Some Problematic Circuits 119
3.3.2 Synchronous Sequential Circuits 120
3.3.3 Synchronous and Asynchronous Circuits . 122
3.4 Finite State Machines 123
3.4.1 FSM Design Example 123
3.4.2 State Encodings . 129
3.4.3 Moore and Mealy Machines 132
3.4.4 Factoring State Machines . 134
3.4.5 Deriving an FSM from a Schematic . 137
3.4.6 FSM Review 140
3.5 Timing of Sequential Logic . 141
3.5.1 The Dynamic Discipline 142
3.5.2 System Timing 142
3.5.3 Clock Skew . 148
3.5.4 Metastability 151
3.5.5 Synchronizers . 152
3.5.6 Derivation of Resolution Time 154
3.6 Parallelism 157
3.7 Summary . 161
Exercises 162
Interview Questions 171
Chapter 4 Hardware Description Languages 173
4.1 Introduction. 173
4.1.1 Modules 173
4.1.2 Language Origins . 174
4.1.3 Simulation and Synthesis . 175
4.2 Combinational Logic. 177
4.2.1 Bitwise Operators . 177
4.2.2 Comments and White Space 180
4.2.3 Reduction Operators . 180
4.2.4 Conditional Assignment 181
4.2.5 Internal Variables . 182
4.2.6 Precedence 184
4.2.7 Numbers 185
4.2.8 Z’s and X’s . 186
4.2.9 Bit Swizzling 188
4.2.10 Delays 188
4.3 Structural Modeling 190
4.4 Sequential Logic . 193
4.4.1 Registers 193
4.4.2 Resettable Registers 194
4.4.3 Enabled Registers 196
4.4.4 Multiple Registers . 197
4.4.5 Latches . 198
4.5 MoreCombinationalLogic. 198
4.5.1 Case Statements . 201
4.5.2 If Statements 202
4.5.3 Truth Tables with Don’t Cares . 205
4.5.4 Blocking and Nonblocking Assi
展开全部
数字设计和计算机体系结构 -(英文版.第2版.RRM版) 作者简介
【加照片】
莎拉 L. 哈里斯（Sarah L. Harris） 内华达大学电子与计算机工程系副教授，拥有斯坦福大学电子工程博士学位。她曾在惠普、圣地亚哥超算中心、英伟达公司和微软亚洲研究院工作，擅长计算机体系结构设计和系统设计。
戴维·莫尼·哈里斯（David Money Harris） 哈维玛德学院工程系教授，拥有斯坦福大学电子工程博士学位。他曾在英特尔公司从事Itanium和Pentium II处理器的逻辑和电路设计，并曾担任Sun Microsystems、惠普、Evans & Sutherland等设计公司的顾问，获得了12项专利。
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